Multiplex system for elevator control

ABSTRACT

A system of transmitting control and indicator signals between elements of an elevator system such as between a car movable along a hatch-way and car control or supervisory equipment wherein the signals are coded and transmitted in multiplexed form over a single transmission line. A two station system between a car and a fixed location is illustrated with a transmitter and receiver at each station. The coded signals are time sequenced so that all signals are considered cyclically.

United States Patent I [111 3,782,504 Billmaier et al. Jan. 1, 1974 [54]MULTIPLEX SYSTEM FOR ELEVATOR 3,203,506 8/1965 Cummins 187/29 CONTROL 4[75] Inventors: Joseph F. Billmaier; Gordon P. j 'f" "f E 323 b th f T 1d ssls an xammern n, Sprague o O 0 e o lo Attorney-Wilson & Fraserv [73]Assignee: Reliance Electric Company, Euclid,

Ohm 57 ABSTRACT [22] Ffled: 1972 A system of transmitting control andindicator signals 1 1 pp 314,918 between elements of an elevator systemsuch as between a car movable along a hatch-way and car con- [52] U CL187/29 R 340/19 trol or supervisory equipment wherein the signals are[51] Int. Cl

' 3/00 coded and transmitted in multiplexed form over a sinl gletransmission line. A two station system between a [58] Field of Search187/29, 340/19, 21

car and a fixed location is illustrated with a transmitter [56]References Cited and receiver at each station. The coded signals areUNITED STATES PATENTS time sequenced so that all signals are consideredcyclically. 3,662,861 5/1972 White et a1. 187/29 3,519,105 7/1970 Geil187/29 34 Claims, 6 Drawing Figures i TRANSMITTER RECEIVER M 1 .E 115 il 1 L MULTIPLEXER 1 e BIT OUTPUTS i l LAT.CH 12s l 1 1 11 52131? 1BINARY T0 DECODER 1 I DECIMAL I24 1 DECODER 1 I 1 121 I I 122 v 17 I 1123 LINE LINE START DRIVER I RECEIVER RiNG 11a COUNTER COUNTER l I 1 lCLOCK 1 l 116 1 1 w PATENIEH'JM 1m.

sum 1 or 4 IF-IGQI ALIMIT 'BLMIT (TRUE) E. (FALSE) SR (TRUE) (TRUE) FIG00 (FALSE) 7 MULTIPLEXER STATION "5 TRA SMI TER RECEIVER MULTIPLEXERSTATION "A TRANSMITTER RECEIVER PATENTEDJAN 1 I91 sum 3 OF 4 ABCPATENTEUJAN 11974- sum u nr 4 1 MULTIPLEX SYSTEM FOR ELEVATOR CONTROLDESCRIPTION OF THE PRIOR ART In a modern elevator system there is therequirement for communication of a large number of separate control andindicator signals between the movable elevator car and a stationaryelevator controller and between various stations such as indicatorpanels and controls and between controllers and system supervisorycontrols. Heretofore, this communication has been accomplished byproviding one or more cables with individual wires for each signalsource to electrically link the stations such'as the traveling cablebetween the car and the controller. As more features are added to theelevator system these cables become progressively more heavy and costlyand less flexible.

In an attempt to solve this problem the prior art has utilized thetransmission of different frequencies of a single transmission line.Representative systems are disclosed in Cummins Patent entitled RadioCommunication Means Between Elevator Cage and Motor Control" issued as3,203,506 on Aug. 31, 1965 and Geil U.S. Pat. No. 3,519,105entitledVehicle Control issued July 7, 1970. Each control signal is assigned adistinct frequency, either just a carrier or a carrier with audiomodulation, which is generated by an oscillator At the receiving end ofthe transmission line there are filters and detectors for each signal.

Although the frequency technique eliminates the bulky flexible cable italso has the disadvantage of being complex and costly. Each controlsignal must have its own oscillator, filter and detector. Where thereare a large number of signals involved the available frequency spectrummay dictate bandwidth .and spacing that requires the use of relativelyexpensive components.

SUMMARY OF THE INVENTION I Communication between components of anelevator system such as the elevator car and the elevator controller isachieved by coding binary signals and transmitt ing them along a commondata line in multiplexed form. Conventional elevator control andindicator siglocal receiver has received its full multiplex signalsequence and the local transmitter has sent its full multiplex signalsequence the local transmitter is cycled to again read and transmit itsmultiplex signal sequence.

Signals are represented as a true or false state for each item sensed.In the example, a 32 word multiplex signal sequence is employed. A truecondition for the word is signified by a short interval logic 1 and afalse." condition is represented by a longer interval logic 1 Each wordis made up of four bits defined by a transmitter clock such that thefirst and fourth bits are always a logic the second bit is always alogic 2 1 and the third bit is a logic 0 if the condition is true and 1if the condition is'false.

The receiver section of each multiplexer is sequenced by a counter whichis clocked from its opposite transmitter by each word it receives by therising leading edge of the signal during the second bit i'nterval of theword. Decoding of the word is by means of a timer which senses the logicstate of the received signal during the third bit interval of the word.

, Transitions in input conditions for a signal during that portion of asignal cycle in which that signal is being transmitted is prevented fromaltering the transmitted signal. A check of the input at the beginningof the signal transmission forits word sets a latch and prevents achange in the logic 1 duration dictated at the setting of the latch.Thus, changes in a condition represented by a word are indicated onlyduring the next transmission of a multiplex signal cycle at the timesignal for that word is read.

Synchronization of a transmitter. multiplex signal cycle and the inputsit reads with the receiver multiplex signal cycle and the output latchesit. sets .is sensed by the completion of a local transmitter multiplexsignal cycle and coincidence of completion of a local receiver multiplexsignal cycle. The failure to achieve a coincidence of completed signalcycles for an excessive interval resets the transmitter to forcesynchronization where the transmitters of each station are arranged sothey always complete their signal cycles and upon completion alwaysenable their local receivers.

DESCRIPTION OF THE DRAWINGS 7 FIG. 4 shows a portion of a multiplexsignal sequence I including several coded signals for false andtrueinputs to the multiplex unit;

FIG. 5 is a schematic representation of a transmitter section which maybe employed in the multiplex unit of FIGS. 2 and 3; and 1 FIG. 6 is aschematic representation of a receiver section according to thepreferred embodiment of the multiplex unit of' FIGS. 2 and 3.

DESCRIPTION OF THE PREFERRED EMBODIMENT utilized with any number ofelevator cars. Elevator cars 20 and 21 are connected to one end ofcables 22 and 23, while the other end of each cable is connected tocounterweights 24 and 25. The cables are placed over sheaves 26 and 27which are rotated to raise and lower the elevator cars. The sheaves areattached to the output shafts of motors 28 and 29. Generators 31 and 32have their armatures electrically connected to the armatures of motors28 and 29 to form a well-known Ward-Leonard system of speed control-f9)each elevator car. Each motor and generator combination receives controlsignals from controllers 33 and 34. These controllers determine themovement of the elevator car in response to control signals in the formof car calls, hall calls and other running signals. Where two or moreelevator cars are to service the same landings, a supervisory control 35is provided to determine, for example, the distribution of the cars andwhich controller will respond to a hall call.

It is apparent that there must be connections between the elevator carand its controller and the landings and the supervisor in order totransmit the necessary control signals. For example, in the five floorbuilding shown in FIG. 1, elevator car contains a panel 36 with fivepushbuttons, one for each floor, with which to register car calls. Thecar also includes means sensing its location alongthe hatchway such asan inductor notching switch 40 responding to the cars passing criticalpositions in the hatchway and controls responsive to the position of thedoor 50 providing a closure for its entry from the landings it serves.In'order to transmit a car call, a door control signal,or a car positionsignal to the controller, previous systems have utilized a travellingcable containing separate wires for each switch responsive to thosefactors. The present invention reduces the wires required fortransmitting control signals' to a twisted pair no matter how manyfloors are contained in the system. The pushbuttons on panel 36 are theinputs via leads 36-1 as are door control leads 50-1 and car positionleads 40-1 to multiplexer unit 37 mounted on elevator car 20. Thesesignals are converted to coded signals and are transmitted on twistedpair 38, which may be cabled with power and telephone conductors to thecar to a similar multiplexer unit 39 located near controller 33. Thecoded signal is decoded and sent to controller 33 which will stop theelevator car at the proper floor.

Multiplexers may also be used to send hall calls to the supervisor. Eachfloor except the tenninal floors has a set of up and down hall callpushbuttons 41. Thus, according to prior practice separate lines fromeach floor to the supervisor would be required. By utilizingamultiplexer unit, hall calls from several adjacent floors can be codedand transmitted on a twisted pair to another multiplexer unit at thesupervisor. in FIG. I the top two floors have hall call pushbuttons 41connected to multiplexer unit 42. Coded signals are transmitted ontwisted pair 44 to multiplexer unit 46 where the signals are decoded andsent to supervisor 35. The first, second and third floor hall callpushbuttons 41 are connected to multiplexer unit 43 which transmitscoded signals on twisted pair 45 to multiplexer unit 47.

A further example of utilizing the present invention to reduce wiring isillustrated by the indicator panel in the lobby. Indicator panel 48 hasa series of lighted numbers which present a visual display of elevatorcar location and call registrations to persons waiting for the car. Carposition signals and hall call signals from supervisor 35 are coded bymultiplexer unit 49. The coded signals are transmitted on twisted pair51 to multiplexer unit 52 where the'signals are decoded and sent toindicator 48.

In many cases it may be desired to transmit signals in both directionsbetween two locations. In the case of elevator car 20, car locationsignals from controller 33 may be used to actuate a visual indicator inthe car (not shown). Therefore, each multiplexer unit contains atransmitter and a receiver which are alternately activated. When thetransmittor in unit 37 is sending,the receiver in unit 39 is enabled.After a predetermined period of time or the transmission of apredetermined pulse train to the receiver in unit 39, the transmitter in39 is enabled as is the receiver of unit 37. FIG. 2 is a block diagramof a basic multiplexer unit and FIG. 3 represents a pair of coupledmultiplexer stations. Transmitter section 111 and receiver section 112are connected in parallel to data lines 113, typically a twisted pair.

The transmitter 11 1 has as inputs a start signal on line 118 and aplurality of input lines 114 which are connected to various controlsignal sources. As in FIG. 1 these inputs could be from the car callpushbuttons on panel 36, leveling switches as 40, door limit switches,door safety switches, manual switches for door control, andattendant-automatic service switches all on the car. When a switch isactuated, the signal is multiplexed, transmitted to the receiver sectionof the multiplexer unit at the elevator controller, set into the properoutput to the controller, and processed by the controller.

In the case of a car call, a signal from the controller to illuminatethe light of the car pushbutton for the call which is registered. ismultiplexed at the controller multiplexer unit, transmitted to thereceiver of the elevator car multiplexer unit and set intothe properoutput for the pushbutton light. Similarly, the controller can sendother signals to the car such as position indicator controls, direction,arrows, and open and close door signals. 1

As will be set forth in more detail the multiplexer transmitters 111each include means to read the signals imposed on a plurality of inputsin a predetermined order. Normally, the read sequence for a station isre peated following the completion of a receive cycle for that stationwhich follows the read cycle. The signals are coded as words at theinitiation of their individual read intervals and are transmitted to thereceiver 112 of the opposite multiplexer station over a transmissionline 113. The receiver at the opposite station is sequenced by thereceived word signals to apply decoded individual word signals to signalstorage means or latches having outputs. The sequence of application ofsignals to the storage means and outputs corresponds to the sequence ofsignal inputs read at the opposite station transmitter. Coupled to theoutputs are the utilization circuits for the respective signals, whichcircuits can be conventional for control of the car and its signals.

The start signal on line 1 18, which may be an indication that the powerhas been turned on, activates a clock I16 and enables a ring counter117. The clock, which is an oscillator running at a predeterminedfrequency, generates a train of pulses. Those pulses are counted by ringcounter 117 which in turn produce a binary output count to binary todecimal decoder 119. The decimal count from decoder 119 steps themultiplexer so that each input signal appears at the line driver 121 ina definite time sequence. The line driver I21 transmits the multiplexedsignals over data lines 113 to the receiver section of another multiplexunit. When the last coded signal has been transmitted, the clock 116 isinhibited and the receiver section 112 of the car multiplexer unit isenabled.

Inputs on input lines 114 are in the form of the presence of or absenceof a voltage of a predetermined magnitude. The presence of the voltageindicates a true signal or logic 1 while the absence of the voltageindicates a false signal or logic 0. The input signals are coded in theform of a group of four pulses. As shown in FIG. 4, false is representedby a 0 pulse, two contiguous 1 pulses and another 0 pulse. A true signalis represented by a 0 pulse, a single 1" pulse and two more 0 pulses.The first and last pulses of the group serve to condition the receiverto readand time the middle two pulses which carry the information. Inreceiver section 112 each group of four pulses'is received by linereceiver 122 and pulses advances ring counter 123 one count. The outputof the ring counter is in binary form and is converted to a decimalnumber by binary to decimal decoder 124. The output of the decoder isutilized to sequence the 8-bit latches 125 so that information from theline receiver 122 is placed on the proper output line of a plurality ofoutput lines 126. After the last group of pulses is read, the ringcounter 123 resets the ring counter 117 of. its

multiplexer unit and the transmitter section 1 11 of that unit beginstransmitting again.

A typical encoding for a simple one car system employs multiplexer unitshaving a 32 word capacity such that the car unit, termed multiplexerunit A in FIG. 4, transmits a signal cycle of 32 words of true or falsesig-' nals each of four pulse lengths in the sequence:

door open manual switch safe edge switch door protection switch I doorlimit, open door limit, closed leveling switch up leveling switch downnotching switch up notching switch down first floor car call secondfloor car call third floor car call fourth floor car call any car callThe receiver of the multiplexer unit at the controller, termedmultiplexer unit B, is sequenced to actuate counterpart controls atthecontroller for the above signals in the order set forth. Conversely,the transmitter of multiplexer unit B has a predetermined sequence ofsignals for which the receiver of multiplexer unit A is correspondinglysequenced. In the example, the controller-to-car signals are sequencedfor the individual car call register lights as the firstfive words, thena blank or spare word, then the five position indicator light signalsfor car position, then seven spare words, then door open signal, doorclose signal, position indicator up direction, and position indicatordown direction. These signals are directed in the sequence of theirreceipt to actuate controls for call registration indicators, positionindicators and door controls to open and close the car doors, all ofwhich are on the car.

An initial portion of a car-to-controller signal issued by thetransmitter of multiplexer unit A is illustrated in FIG. 4 wherein thefirst bit has a long pulse indicating the door open pushbutton, D0, inthe car is not operated during that signal sequence. The safe edgeswitch SE signal is also represented by a long pulse indicating no safeedge operation. An obstruction in the door path operated the doorprotection switch, for example a safe ray (not shown) which sensesinterruption of a beam of radiant energy across the door path, toproduce a true signal or short pulse, SR. At the moment represented, thedoor is partially closed since the door open limit, the A limit, istrue, and it has not fully closed since the door close limit, the Blimit, also is true. The remainder of the sequenced signals for thecar-tocontroller transmitter cycle has not been shown.

FIGS. 5 and 6 are schematic representations of the transmitter section111 and receiver section 112 of FIG. 2. In FIG. 5, 141 represents aninverter which converts a logic 1 at its input to a logic 0 or a logic 0at its input to a logic 1. Element 142 is typical of a NAND gate whichhas a 0 output when both inputs are at 1 and a 1 output for any othercombination of inputs. Element 137 illustrates the symbol for a NANDgate in negative logic.

Element 158 is typical of a NOR gate which has a 1 output when bothinputs are 0 and a 0 output for any other combination of inputs. Element161 is typical of the symbolfor a NOR gate in negative logic.

Element 169 is a NOR flip flop comprised of two NORs each with theoutput coupled to an input. of the other. When both inputs 1 and 2, areat 1 and both outputs, 3 and 4, are at 0. When the inputs are ofopposite signals then output 3 will be at the same as input 1. If bothinputs are at 0," one output will be 1 and the other will be 0 dependingon which input switched to 0 first. When input 1 switches to 0 firstoutput 3 will be 1.

Element 131 is a typical multiplexer section which has eight input lines1 through 8, three count input lines A, Band C, and enable input 9-andan output 10. When enable 9 is at 0 the signal on output 10 is theopposite of the one selected input signal on lines 1 through 8. Acombination of signals on the three count input lines selects one of theinputs to be represented at the output. For example, if all three countinput lines A, B and C are at 0 then input line 1 is selected and a 0"on line 1 will produce a 1 at output 10. By providing a binary count ofzero to seven in sequence at the count input lines A, B and C inputlines 1 to 8 will be read in sequence.

Element 143 is a typical 4-bit binary up counter with four output linesA, B, C and D. Line 1 is a parallel enable input which when providedwith-a 1" input produces a one bit count on the output lines for each 1pulse at the input shown connected to line 129. A 0 on line 1129 enablesthe counter and a 1 transfers the data to the output lines. Leads 2 and3 are a count enable which enables the counter when. they have a 1"input. Lead 4 produces a 1 only if lead 3 is a 1" and all outputs areat 1. This allows the counters to be used in series. A master resetinput is connected to line 128 and a 0 will clear all the outputs.

Element 153 is a binary to decimal decoder. A 0 on input line D enablesone of the four output lines 1 through 4. For example, if lines A, B andC are at 0 output line 1 will beat 0 and the other output lines will beat 1. If line A is changed to 1,'output line 2 is at 0 and all othersare at 1. With inputs C and D grounded, the binary signal on lines A andB determines which output is enabled and thus which of multiplexersections 131, 132, 133 or 134 is enabled.

Line driver 121 is utilized to transmit the coded signals of FIG. 4.Element 157 is a NAND gate and when all inputs are at 1 output 4 is at0. A 0 on any input will produce a 1 at output 4. Output 5 is aninverting output which will have the opposite signal from line driverand is grounded through a resistor. These resistors permit the linedrivers of the local and remote multiplexer to be connected to the sametransmission line 113 and to function as wired ORs as independent inputsto a common output.

In FIG. 6 line receivers 122 receives the coded signals from data lines113. Element 199 is an amplifier which produces a 1 for a.1 signal onthe input and a signal on the input and a 0 for a 0 signal on the inputand a 1 signal on the input.

Element 204 is an 8-bit addressable latch. A combination of signals onthe inputs connected to lines 227, 228 and 229 select one of eightoutput lines 126. If a 0 is present on the enable input E the decodedsignal from the line driver 122 will be stored on the selected outputline 126 corresponding to an input line to the then effectivemultiplexer section and a line of the transmitter.

Element 211 is a NAND flip flop which has a l on each output when theinputs are at 0.. When the inputs have opposite signals output 3 will bethe same as input 2 and output 4 will be'the same as input 1. When bothinputs are at 1 one output will be at 1 and the other at 0 depending onwhich input switched to 1 first. When input 1 switches to 1 first output3 will be 0.

' Element 193 is a monostable multivibrator consisting of an OR gate, aflip flop-and a timing network. The OR gate has a regular input 1 and aninverting input 2 and its output is the input to the flip flop. Byplacing a l on the clock input C12 the signal at the OR output willdetermine the Q and Q outputs for a time period determined bythe timingnetwork of resistor 194 and capacitor 195. A 0 from the OR outputproduces a 0 ft O and a 1 from the OR output produces a 1 at Q.

In FIGS. 5 and 6 the terminals of various devices have been numbered orlettered and each device has a reference number. When referring to adevice terminal it will be set forth as a suffix to the reference numberseparated therefrom by a dash, such as terminal 1 of NAND 137 in FIG. 5designated as 137-1.

The general scheme of operation of the transmitter section 111 as shownin FIG. 5 is to sequentially consider or read each input 114 throughsections 131 to 134 of the multiplexer 115 using the C and D outputs ofcounter section 143 and the A output of counter section 144 to enable,by binary code to the A, B and C inputs of multiplexer sections 131 to134, a corresponding one of each of the inputs 1 to 8 of the multiplexersections 131 to 134. Counter section 144 also individually enables themultiplexer sections 131 to 134 by binary coded signals from its B and Coutputs to the A and B inputs of binary-to-decimal decoder 153. The Aand B outputs of counter section 143 control the logic which generates awide pulse for a false" state at the then effective input lead 114 and anarrow pulse for a true" state.

Counter 117 is reset when the receiver section 112 of its multiplexerstation has received a full multiplex signal cycle train of signalwords. This is indicated as a master reset signal on lead 147 from thereceiver section ll 12. The clock 1 16 driving counter 117 is freerunning until inhibited by an indication of the completion of amultiplex signal cycle transmission to satisfy gate 135. When gate issatisfied it also enables the multiplexer receiver section of itsmultiplex station by signals on leads 173 and 174.

A multiplexer signal cycle is transmitted as thirty-two words eachcomprising 1 four pulse intervals of clock 116. A true word is made, upof contiguous pulses of logic 0-1-0-0 while a false word is contiguouspulses of logic 0-1-1-0. These words are transmitted to transmissionline 113 from line driver 121 and are encoded by NAND 163 for a trueword and NAND for a false word. Flip flop 169 is set irrevocably duringthe initial read portion of a word interval by the then current true orfalse state on the input lead 114 being read by the multiplexer 115.This enables NAND 163 and disables NAND 165 for a true signal, andenables NAND 165 and disables NAND 163 for a false signal. NAND 1563 canbe gated only during the second counter pulse interval of each wordinterval by gating NOR 161 when counter section 143 issues a 1 on its Aoutput and a 0 on its B output. NAND 165 can be gated only during thesecond and third counter pulses. During the first pulse NOR 158 receives0 from both the A and B counter outputs and inhibits NAND 165. Duringthe fourth pulse NAND 159 receives a 1 from both the A and B counteroutputs and inhibits NAND 165. During the second and third pulsesoutputs A and B of counter 143 are in opposite states to enable NAND 165from NOR 158 and NAND 159.

Flip flop 169 is set at the beginning of each word interval during theperiod the counter section 143 outputs A and B are both 0 as signifiedby NOR 158 to NOR 171 to make NOR 171 responsive 'to the signal fromNAND 156 and thus the state of the effective multiplexer input 114. Itis reset at the time a 1) appears from NAND 159 when both the A and Boutputs of counter section 143 are at 1. Any change of the signal atinput 114 to NAND 156 has no efiect after the first clock pulse intervalof the word interval since NOR 171 is inhibited and cannot change thestate of flip flop 169. 1

FIG. 5 is a schematic representation of transmitter section 111 of FIG.2 for each multiplex unit. Hnputs from various control devices appear oninput lines 114 in the form of a 1 or a 11". A start signal on line 118enables ring counter 117 to receive a train of pulses from clock 116.The number of pulses counted is presented in binary form to word coder158, 159 and 161, the reader-multiplexer sections 131, 132, 133 and134., and the binary to decimal decoder 119. Decoder 119 enables each ofthe multiplexer sections 131 to 131 of 1 15 in order. As eachmultiplexer section is enabled the binary count enables each inputline114 in sequence. The signals on the input lines as to an A unit are readand are coded and transmitted over date lines 113 by line driver 121 tothe receiver section of another multiplex unit, the B unit. After thelast input signal has been sent by the A unit, signals on lines 173 and1'74 activate receiver sections 1 12 of its multiplexer unit, the Aunit, to receive signals from the transmitter of the other multiplexunit, the B unit. When receiver section 112 of the A unit has completedreceiving, it produces a signal on line 147 to enable the transmittersection 111 of its multiplexer unit, the Aunit. Lines 128 and 129 allowexternal resetting of all ring counter outputs and injection of clockpulses for test purposes.

The input lines 114 are separated into four groups of eight lines eachwhich are the inputs to multiplexer sections 131, 132, 133 and 134. Theparticular multiplexer section is selected by the binary to decimaldecoder 119 while the line is selected by a signal from the ring counter117.

The clock 116 consists of NAND 136, NAND 137, resistor 138 and capacitor139. During the counting cycle of ring counter 117 at least one of theinputs to NAND 135 will be until the maximum count is reached. Thismeans that the output of NAND 135 is 1 until all inputs become 1. Theoutput 1 is changed to 0 by inverter 141 and appears as the input atlead 137-1 of the clock 1 16. This 0 produces a l on output lead 137-3of NAND 137 and since the input leads 136-1, 2, 3, 4 of NAND 136 aretied together, the output lead 136-5 is at 0. This output is fed back tothe input of NAND 136 by resistor 138 with a time delay caused bycapacitor 139.

With output lead 136-5 at 0 capacitor 139 discharges through resistor138 since output 137-3 cannot provide enough current to keep it fromdoing so. Output 136-5 then changes to 1 and capacitor 139 charges upagain. The cycle repeats itself providing a pulse train at a ratedetermined by the values of the resistor 1 38 and the capacitor 139.

The pulse train appears at input lead 142-2 of NAND 142 which in turnprovides the input to the clock pulse lead of 4-bit binary up counters143 and 144 which comprise ring counter 117. Line 118 provides a 1 oninput lead 142-1 through resistor 145 and the positive power supply. Ifthe input to line 118 is grounded, for example through an externalrelay, the resultant 0 signal on input lead 142-1 will cause the output142-3 to always be 1. Therefore, the pulse train from the clock 116 willnot be passed to the ring counter 117. When the ground is removed, theoutput will be 1 when lead 142-2 is 0 and 1) when lead 142-2 is f 1.During the time a 0 is present at the clock pulse inputs for counters143 and 144, data can enter and it is transferred to the outputs whentheclock pulse goes to 11. Leads 143-1 and 144-1 are the parallel enableinputs and when they are connected to the positive power supply as shownthere will be a one bit shift in the'eounter output for each clock pulseinput.

The counters 143 and144 also have a count enable which permits the clockpulse to activate the counter only if leads 2 and 3 are both at 1." Oncounter 143 the leads 143-2 and 143-3 are both connected to the positivepower supply so counter 143 will be counting all the time. Counter 144however has leads 144-2 and 144-3 connected to lead 143-4. Lead 143-4 isonly 1 when lead 143-3 is 1 and all output leads A, B, C and D are 1.Therefore, counter 144 will not count until counter 143 has registered15 counts. The next count changes the front output of counter 144 to 1and sets all the outputs of counter 143 to 0. This puts a 0 on lead143-4 and counter 144 will not register another count until counter 143has registered 15 more counts. When l27 pulses have been registered allthe counter outputs will be at 1 and the output NAND 135 will changefrom 1" to 0. The input 137-1 will be 1 and the 1 from output 136-5 isthe input to 137-2 producing a 0 at 137-3 and stopping the clock. The

clock will only start when the ring counter117 is reset. Line 118 isalso connected to input lead 146-1 of NAND 146 which provides the masterreset signal to the counters 143 and 144. A 0 at the master reset clearsall the outputs of the counters. Again, if line 118 is grounded NAND 146can only provide a 1 so the removal of the ground enables NAND 146. Thesignal to reset the counters is applied to line 147 from the receiversection 112 as a 0 and is changed to a 1 by inverter 148. Now inputleads 146-1 and 146-2 both are at 1 which produces a 0 output on lead146-3 to reset the counters. This reset occurs when the receiver section112 has completed receiving its data and the transmitter section 1 1 1is ready to begin a transmission.

Lines 149, 151 and 152 are the 4, 3 and 16" count outputs from thecounters 143 and 1. These outputs are used to control the selection ofinput lines 114, eight of which go to each multiplexer section. Usingmultiplexer section 131 as representative of the four shown, it hasinputs 131-1 through 131-8, enable input 131-9 and output 131-10. Whenthe enable input 131-9 is at 0 the output 131-10 represents the inverseof the input signal on the lead 114 selected for reading by thecombination of signals on output lines 149, 151 and 152. For example,when the output lines 153-1 to 153-4 are all at 0, output 131-111 is 1if the input line 114 selected is 0."

' The ring counter 117 changes output when a 1 from 142-3 or 129 appearsat the clock pulse input. Since the output of clock 116 is 1 when thering counter is reset the ring counter will not record a count until thesecond 1 is produced by the clock. Therefore, during the four pulses ofeach word interval as the counter goes from binary zero to a binarythree lines 149, 151 and 152 remain at 11. This combination of inputs tothe A, B and C terminals of the multiplexer sections selects the firstinput line for each multiplexer section. During the next four pulsesline 149 and the A inputs are 1 and the second line in each multiplexersection is selected for reading. As the ring counter progresses, eachinput line is selected in turn and is held for four counts until 32 wordintervals have been generated. Therefore, during'the 128 clock pulsesrequired for one cycle of the ring counter, the input lines can beselected four times. However, each multiplexer section has an enableinput that receives signals from a binary to decimal decoder 153. Thesequencing of the decoder limits each line to one reading during a ringcounter cycle.

The 32" and 64 count outputs from the ring counter are inputs 153-A and153-B. inputs 153-C and 153-D of the decoder are tied to ground so thata 0" is present. During the first thirty-two pulses all the inputs todecoder 153 are at 11 which puts a 0 on enable input 131-9 and a 1 onall the others. Therefore, multiplexer section 131 reads all of itsinput lines in order. During the next 32 counts, input 153-A is at 1while the others remain at 1 1 which puts a 0" on enable input 132-9 anda 1 on all the other enable inputs. After 128 pulses all fourmultiplexer sections have read each of their eight input lines one time.

The outputs of the multiplexer sections are the inputs to NAND 156. Aslong as one of the inputs is 11 the output is held at 1 and it only goesto 0" when all inputs are 1. Since the output of a multiplexer sectionis 1 when it is not enabled three of the inputs to NAND 156 will alwaysbe 1. The fourth input will be the output of the multiplexer sectionthat is enabled which is the inverse of the input line 1 14 that isselected for reading at that moment. Therefore, if during the first fourclock pulses input line 131-1 is at 1, output 1131- will be at 0 makingthe output of NAND 156 1. Thus the signal on the selected one of inputlines 114 will appear at the output of NAND 156.

The line driver 121 has three inputs which are connected to NAND 157.input 157-3 receives the output from NAND 135 which is 0 only after thelast pulse in the ring counter cycle thus the line driver is enabledduring a transmission cycle and inhibited upon termination of that cycleuntil the next transmission cycle. The other two inputs receive signalsfrom the signal word encoding or defining logic network which combinesthe output signal from NAND 156 and the word defining 1 and 2 countoutputs from the ring counter. The 1 and 2 count outputs are the inputsto NOR 158, NAND 159 and NOR 161. Before the first pulse in the ringcounter cycle, all ring counter outputs are at 1. A reset pulse on line147 at the beginning of a transmission resets the ring counter outputsto 0. This is the zero pulse interval which puts leads 158-1, 158-2,159-1, 159-2, 161-1 at 0 and lead 161-2 at 1 since the 0 is changed byinverter 162.

Each word interval of four counts is defined by a first clock intervalin which the A and B outputs of counter 143 are logic 0, a secondinterval in which A is at 1 and B is at 0, a third interval in which Ais at 0 and B is at 1 and a fourth interval in which A and B are both 1.Thus the first word in a transmitted signal sequence is encoded duringbinary count zero through three, the second word during binary countfour through seven, the third word is encoded during binary count eightthrough eleven, etc.

are l. Inverter 168 makes 169-1 0 so that the set flip flop is enabledfor transfer of state if a 1 is applied at 169-2. inverter 164 makes171-2 0 so that NOR 171 is responsive to invert the signal from NAND 156and the active input 114. if during the initial pulse interval NAND 156issues a 1 for a true signal, 169-2 remains 0 and the latch holds 169-41 and 169-3 0. If NAND 156 issues a 0 for a false signal 171-3 and 169-2transfer to a 1 and the latch changes 169-4 to 0 and 169-3 to 1.

During the second and third pulse intervals of the word encoding periodNOR 158 is inhibited by a 1 on lead 158-2 and 158-1 respectively, sothat 158-3 The initial logic 0 of each encoded wordis developed on thenon-inverting output, the Aline of the transmission line 113, bycoincident l s to the input of NAND 157. With 143 -A and 143-8 both 0,the 1 and 0 input to NOR 161 produces a 0 output on lead 161-3 which isthe input lead 163-2 of NAND 163. The 0 at NAND 163 makes output lead163-3 go to 1 which is the input at lead 157-2 of the line driver. The 0inputs to NOR 158 produce a 1 output which is changed to a .0 byinverter 164 and is the input for lead 165-1 of NAND 165. This producesa 1 output at 165-4 which is input 157-1. Therefore, all inputs to theline driver are a 1 producing a 1 from inverting output 157-5 to lead113-8 and a 0 from output 157-4 through amplifiers 167 and 166 therebytransmitting a 0 on data line 113-A.

In order to avoid transmission of signal transistions which occur duringthe transmission of a word, transmitter 1 1 is provided with a latch forthe signal from the active input lead 114 which is set during theinitial clock pulse interval of each word is maintained through thesecond and third pulses, and is reset in the fourth clock pulse intervalof that word. Flip flop 169 provides that latch by being set to issue a1 at 169-4 and a 0 at 169-3 for a true input at the lead 114 being readand being set to issue a 1 at 169-3 and a "0" at 169-4 for a falseinput.

In the set state flip flop 169 has 169-1 at 1 and 169-2 at 6" so that169-3 is 0 and 169-4 is 1. The initial pulse interval of each wordimposes 0" on 158-1, 158-2, 159-1 and 159-2 so that 158-3 and 159-3holds a 0 to hold 171-2 1" to hold 169-2 0 in the face of any change on17 1-1. Thus flip flop 169 retains the state established during theinitial interval over the second and third intervals.

Reset of the flip flop during the fourth pulse interval of each wordencoding period is accomplished through NAND 159 and inverter 168. Atthe time 143-A and 143-13 are 1", 159-3 is 0 and 169-1 is 1".158-3 is 0so that 171-2 is1and 171-3 to 169-2 is 0.This

insures 169-3 is 0 and 169-4 is 1.

Assuming that input line 114 to 131-1 has a 0 input, the output of NAND156 will be 0 during the time the ring counter counts the zero" pulseinterval of the word cycle. The 0 output from inverter 164 to input171-2 enables NOR 171 and the 0 on input 171-1 produces a 1 at output171-3. When the one pulse interval is counted, input 158-2 becomes 1changing outputs 158-3 to 0 and changing input 171-2 to l. The 1 oninput 171-2 will produce a 0 at output 171-3. The change of state ofoutput 171-3 is delayed by capacitor 172. Therefore, the input signal oninput line 1314 sets flip flop 169 during the one pulse interval. Anychange in the input signal on line 131-1 after the one pulse interval iscounted will not be transmitted until the next transmission cycle oftransmitter section 111 is initiated.

The one pulse interval also changes input -1 to 1. Although input 159-2changes to 1, the output 159-3 remains, at 1 which is the input at165-2f. This 1 is changed to 0 by inverter 168 which supplies the signalto lead 169-1 of flip flop 169. The 1 output from 171-3 changes to 0,but is delayed by capacitor 172. With a ti on lead 169-1 and a1 on lead169-2, output lead 1159-33 is at 1 and lead 169-4 is at 0. The change onlead 169-2 does not produce a change in either output of flip flop 169.

The 1 on lead 169-3 is'the input on lead165-3 making all inputs to 165 1and the output 165-4 a 0". This produces a 0 on output 157-5 and a 1 onoutput 1574. Therefore, at pulse two a. 1 pulse 1 appears on data line113-A.

At pulse three the input leads to NOR 1 58, NAND 159 and NOR 161 reversepolarity which does not change their outputs and consequentlythe 1 pulseremains on data lines 113 during the binary two count. On pulse fourboth inputs to NAND 159 are at 1 so output lead 159-3 become 0" changingthe output of NAND 165 to 1. Inputs 157-2 and 157-3 remain at 1" so theoutput lead 157-5 changes to 1 and output lead 157-4 changes to 0putting a 0" on data lines 113. During the four count period, pulses onethrough four, the data lines were 0 for pulse one, 1" for two pulses,and"0" for the last pulse'producing a signal representing a 0" onthe'input line.

The on output lead 159-3 during the fourth pulse interval is changed toa 1 by inverter 168. The l and 0 inputs to 169-1 and 169-2 produce achange of state in flip flop 169 whereby output lead 169-3 is at 0 andoutput lead 169-4 is at 0. This is the reset of flip flop 169. v

On pulse five (binary count four) input line 114 at terminal 131-2 isselected. Assuming a 1 signal is present, the output of NAND 156 is 1which is the input to NOR 171. During pulses five to eight the inputs toNOR 158,NAND 159 and NOR 161, will change as was detailed above. Theoutputs of flip flop 69 will remain at 0 for 169-3 and at 1 for 169-4.However, at pulse. six (the second pulse interval of this word andbinary count five) when input lead 163-2 is in 1 the input lead 163-1 isalso 1 producing a 0 output at lead 163-3 whichchanges output lead 157-5to 0 and output lead 157-4 to 1. On pulse seven lead 163-2 changes backto .0, output lead 163-3 goes to 1 and the outputs of NAND 157 switchplacinga 0 on data lines 113 which remains there during pulse eight.Therefore, during the four count word encoding period, pulses tivethrough eight, the data lines were 0 for one count, 1 for one count andthe 0 for two counts producing a signal representing a 1 on the inputline and the ring counter has a binary seven output.

FIG. 6 is a schematic representation of the receiver section 112. Codedsignals from a transmitter section are received on data lines 113 byline receiver 122. Ring counter 123 produces a binary count which isutilized by binary .to decimal decoder 124 to select 8-bit latchsections 204, 205, 206 and 207 of latch 125 in order. The binary countalso enables each output line of latch 125 in sequence corresponding tothe reading sequence of inputs 114 at the opposite'station so'that thecoded signals are stored on the output lines 126 as the same signals oninput lines 114.

Each word transmitted to the line receivers 122 clocks the ring counter123 to selectively enable the latches or signal storage means andestablish the decoded signal on its individual output terminal 126.Decoding is accomplished by time synchronism of the state of the wordsignal as high or low during the third pulse interval defined by theclock 116 of the transmitter 111 from which signals are being received.A timer enables the latches 204, 205, 206 and 207 by means of a signalimposed on the enable input E from gates 222, 223, 224 and 225 which aregated only during the third pulse interval of each word. This selectivegating is accomplished by a timer 212 defining an interval greater thanone pulse interval'and less than two pulse intervals of the transmitterclock 116 of the remote multiplex transmitter. Such interval isinitiated on the rising signal of the second pulse interval of the wordso that it expires during the third pulse interval. When it expires itissues a clocking signal to counter 123 and an enabling signal to thelatches to permit the active latch to respond to the then high or lowsignal representing respectively a false or true signal as decoded. Thuscounter 123 is responsive to thirty-two steps in each cycle as imposedbythe thirty-two word intervals of a multiplex signal sequence from thetransmitter.

Receiver 112 of FIG. 6 responds to a train of words transmitted from aremote station transmitter corresponding to transmitter section 111 ofthe multiplexer unit discussedahove. When the transmitter section 1 l1of the local station has transmitted a full multiplex signal cycle trainof signal words, a master reset signal on line 174 resets the countersections 183 and 184. Each word of the signal cycle being receivedbegins with a 0 pulse which produces a 1 from NAND 203. The 1 sets flipflop 211, which in turn resets monostable multivibrator 212. Monostablemultivibrator 212 is then set by the second pulse of each word which isalways a 1 and a timing interval one and one-half of the pulse intervalof the transmitter clock 1 16 of the remote station is produced. At theend of the timing interval, the Q output returns to 0 which enables NANDgates 222 to 225. The-D output of counter section'183 and the A outputof counter section 184 enable, by binary code to the A and B inputs ofbinary to decimal decoder 231, the latch sections 204 to 207. The A, Band C outputs of counter section 183 enable, by binary code on lines227, 228 and 229,a corresponding one of each of the outputs 1 to 8 ofthe latch sections 204 to 207. The signal applied to the selected outputis that present during the third transmitter clock pulse interval ofeach word from lines 113 as indicated by NAND 203.

Completion of the reception of a multiplexer signal cycle gates NAND 185to inhibit further reception of signals in latch by changing the stateof NAND 203 and through NAND 192 resets failure timer 193 while gatingNOR 186. This indicates reception is complete to reset the localmultiplexer transmitter section 1 11 on line 147.

While normal operation involves the alternate advance of a localtransmitter 111 through its predetermined order of reading functions tosend a multiplexed signal sequence to the remote receiver to which it iscoupled by transmission line 133, followed immediately by a signalreception sequence by the local receiver 112 from the remotetransmitter,it is possible, particularly during start up of thesystem,that the transmitter is out of synchronism with the receiver towhich it is sending signals. Such absence of synchronism causes thesystem to lockup since the failure to produce a coincidence of anindication of a completed local transmission utilizing one hundredtwenty-eight pulses through gate of P16. 5 and the indication .ofcompletion of local reception of 32 word periods through gate 135 ofFIG. 6 fails to gate NOR 136 to issue a transmitter reset signal on lead147. in case of a failure to reset a resynchronizing sequence isprovided.

Resynchronization is instituted by failure timer 193 which initiates atiming interval at the beginning of a receiving sequence and is resetupon completion of the receiving sequence. 1f timer 193 is not reset itultimately times out and starts a new transmission sequence. in general,the two station multiplex system of this invention employs liketransmitters and receivers at each station. However, in the case of afailure timer only one timer is required. Hence, the failure controls200 within the dashed boundries of FIG. 6 need be included in only onereceiver, as at the controller station 39, and the car top station 37can be considered to have each of switches 235, 236 and 237 open andeach of switches 238 and 239 transferred from their illustrated positionto the alternative position to couple inverter 188 directly to resetlead 147 through lead 240.

When all the output lines on ring counter 117 of transmitter section 111are at 1, the output of NAND 135 ischanged from 1 to 0 which is invertedto a 1 on lead 174 by inverter 141 and is again inverted to a 0 byinverter 182 and resets counter 123 of the local receiver. The switch insignals on line 173 produces a 1 from inverter 141 on line 174.Capacitor 181 passes a short 1 pulse which is converted to a 0 pulse byinverter 182. This 0 pulse is transmitted to the master reset input ofthe 4-bit binary up counters 183 and 184 comprising ring counter 123.The ring counter is reset with all outputs becoming 0. The outputs ofthe ring counter are also inputs to NAND 185 which produces a 1. That 1initiates failure timer 193 timing interval as will be described. If thecounter 123 reaches a count of thirty-two within the interval of timer193, completion of a signal reception sequence is indicated by transferto a 0 from NAND 185 to NAND 192 to reset timer 193 and the applicationof a 0 to NOR 186 at 186-1 which causes a reset of the transmittercounter to begin anew transmission sequence. Lead 186-2 has a 0 signalfrom line 173 as its input producing 0 output until 186-1 goes 0. Sinceline 186-1 has been at 1 a 0 on output lead 186-3 had no resettingeffect until 181-1 changing .0 made 181-3 1." This signal shift makescapacitor 187 and the inputs to NAND 188 1. The output of NAND 188 is 0.If failure circuit 200 is disconnected, the 0 is applied directly tolead 147 as a reset signal. With failure circuit effective the 0 ischanged to 1 by inverter 189 and is the input to lead 191-2 of NOR 191to develop a 0 at output 191-3 which-resets the counters in thetransmitter section 111 through line 147.

I The 1 from NAND 185 is also present at input I 192-2 of NAND 192. Theother input 192-1 is connected to line 174 and carries the inverse ofthe signal on line 173, a 1. The 1 inputs produce a 0 output at 192-3which is applied to the inverting input 193-2 of monostablemultivibrator 193.

While the 0" is imposed on 193-2 timer 193 times an interval determinedby the time constant of the resistor 194 and capacitor 195, chosen to beexcess of a multiplex signal sequence interval from the transmitter 111.If a full signal sequence is received to transfer 192-2 to 0, the l at193-2 enables input 193-1 to becomeeffective as a reset for failuretimer 193. lnput 193-1 is connected to a clock formed from resistor 196,

capacitor 197 and NAND 198 which generates a pulse train at a frequencygreater than the timing period of monostable multivibrator 193 thatresets the multivibrator to prevent it from timing out.

The 1 on line 174 also enables the line receiver 122 to generate pulseswhich correspond to those transmitted on data lines 1 13 from the remotetransmitter 111. A 1 from amplifier 199 on input 201-2 of NAND 201 andthe 1 on input 201-1 produces a 0 as the input to inverter 202.Therefore, the output of the inverter is the same as the input to theline receiver 122 at non-inverting lead 113-A. The 1 from NAND 185indicating the reception sequence is incomplete enables NAND 203 so thatits output corresponds to the output of the line receiver. The fourpulse false signal word on data line 113 which consisted of a 0" pulse,two 1 pulses and a 0 pulse is now a 1" pulse, two 0 pulses and a 1"pulse at output 203-3. This signal is the to the 8-bit addressable latchsections 204, 205, 206 and 207.

Using the false signal as an example, the first 1 pulse is changed to a0" by inverter 208 and is the input at 209-1 of NAND 209. This producesa 1" at input .211-1 of NAND flip flop 211. Output lead 211-4 will be at1 if input lead 21 1-2 is at 0 or it will not have changed from itsprevious state if 211-2 is at 1. Assuming for the moment that input211-2 is at 1 and the previous state of output 211-4 was 1, monostablemultivibrator 212 has a pulse train at input 212-2 of a frequency whichprevents it from timing out and keeps the Q output at 1. This 1 is theinput to inverters 213 and 214 which produce a 0 output from NAND 215.NAND 216 has all its inputs tied together so there is a 0 at input 217-2of NAND 217. This produces a 1 at input 211-2 which supports the firstpart of the above assumption.

Pulse two from NAND 203 is a 0 which is changed to a 1 by inverter 208placing a 1 on both inputs to NAND 209. The output of NAND 209 changesto 0. Input 211-2 remains at 1 so output 211-4 becomes 0. This 0" atinverting input 212-1 starts the timing of the multivibrator 212 whichis completed in the middle of the third pulse. At that time the Q outputswitches from 1 to 0. This 0 is applied at 218-1 of NOR 218. The outputof NOR 218 is 0 unless both inputs are 0. The 0 is changed to a 1 byinverter 219 but is delayed by capacitor 21 so that momentarily bothinputs are 0 and a 1 pulse results. This pulse enables NAND 222, 223,224 and 225 so that the correct latch is addressed and the third pulseis read.

If the signal is high on line 113-A during the third pulse interval ofthe word currently being transmitted, the signal 203-3 to the latches204 to 207 is low and conversely if it is low at 113-A the signal to thelatches is high at 203-3. The latches store the signal so that thememory and its output 126 addressed at the moment is set in a low staterepresenting the false signal at the then active transmitter input 114or in a high state representing the true state at active input 114 ifthat be the case. Thus, as shown in FIG. 4 if the door open signal D0 isthe transmitted word and is false",the high during the third pulseinterval results in a low on the DO output 126, which is 204-1 in theexample. Similarly, a true safe ray signal SR has a low' third pulseinterval for its word as shown in FIG. 4 and would cause its output lead126, 204-3, to be high.

The change of output Qof 212 to a 0 also is applied to inverters 213 and214. Capacitor 226 provides a delay. After the delay, both inputs ofNAND 215-are 1 and produce a 0 causing the output of NAND 216 to changeto 1. This 1 provides the clock pulse on lead to counters 183 and 1 ofring counter 123.. initially outputs A, B, C and D of 183 and A of 184are all 0. The first clock pulse on 180 produces a binary 1 count as a 1on output 183-A and lead 227, while leads 228, the 2 lead, and 229, the4 lead, remain at 0. These leads provide the address to the latchsections. The 1 on lead 227 is delayed until after the third pulse isread and stored at output 204-1 while the address lines are at 0. Thedelay is provided by capacitor 220 which prevents NAND 216 from changingstate for apredeterrnined time. When the delay is over lead 227 goes to1" and output line 204-2 is selected for storage of the second bit ofinformation. Thus, the latch is addressed prior to being enabled fromgate 222, 223, 224 or 225 and for subsequent words inthe multiplexsignal sequence that address is established during the terminal portionof the preceding word period.

The 8 and 16 count outputs from the ring counter 123 are inputs 231-Aand 231-B of binary to decimal decoder 231. inputs 231-C and 231-D aretied to ground so that they are always 0. During the first eight pulsesall the inputs to decoder 231 are at and the zero count output puts a 0on inverter 234 to produce a 1 at input 222-1 of NAND 222. All othercount outputs of decoder 231 are at 1 thereby inhibiting gates 223, 224and 225. Since NAND 222 is enabled by a 1 on input 222-2 a 0 is appliedto the E input of 2114 which enables latch section 204. As a result, the0 which was the third pulse from the transmitter is placed on the firstoutput line of latch 204. In this way the latches are set in the sameorder as the input signals on.lines 114 were processed by thetransmitter.

The fourth andlast pulse in the group comprising the signal word in themultiplex signal cycle is a 0 which is a 1 at 203-3. This 1 is changedto a 0 by inverter 208 which produces a 1" output from NAND 209. Sincethe Q output of multivibrator'212 is still 0, input 217-2 remains at 1and, with the 1 on input 217-1, produces a 0 on output'217-3. The 1" and0 inputs to NAND flip flop 211 change output 211-4 to 1. This allows thepulse train at input 212-2 to change the Q output to 1 where it willremain until changed by the next group of four pulses.

The 1 at Q of 212 for the reset timer is .the input to inverters 213 and214 and produces a 0 at input 215-1 changing the output to 1. The outputof NAND 216 becomes 1) which produces a 1 from NAND 217 holding NANDflip flop 211 with a 1" at output 211-4 which supports the second partof the previous assumption.

The next group of four pulses will advance ring counter 123 and theinformation will be stored on the second output line of latch section204. When the last group of four pulses is received all the outputs ofthe ring counter will be ,1 changing the output of NAND 185 to 0 andproducing a 0" on line 147 through NOR 186 inverters 188 and 189 and NOR191 to reset the local multiplexer transmitter and start its clock.Failure timer 193 is reset by the 0" at 192-2 to issue a resetting 1" to193-2 so that 6 remains 0 to 191-1. If the receiver fails to respond toits full multiplexer signal sequence by failing to advance its counter123 through a count of thirty-two, NAND gate185 would not besatisfiedand would continue to issue a 1 to NAND 192 at 192-2. This wouldmaintain 192 gated and continue the timing of timer 193. At the end ofthe timer interval output 6 of timer 193 would shift to 1" causing NOR191 to issue a 0 at 191-3 to lead 147 thereby restarting the localtransmitter.

Synchronization of the transmitter of each station with the receiver ofits opposite station is normally maintained by starting transmissionfrom transmitter A to receiver B simultaneously with the start ofreception by receiver B. At the end of transmitter As transmission itstarts receiver A by resetting counter 123, enabling line receiver .122,starting timer 193 through NAND 192 and enabling its reset NOR 186. Ifat that time receiver B has completed its reception it gates its NOR 186to start transmitter B by resetting its counter 117 to enable its linedriver 121 and clock 1 16. This alv temate transmission andreception ateach station continues if the termination of transmission from onestation coincides with the termination of reception by the other.

At times the transmission and reception can be out of synchronization.That is a door open signal DO might be sent as a first word and receivedas a safe edge signal SE, the second word of the multiplex signal cycle.Such loss of synchronization is corrected by the interlocks which startlocal reception when a full word count of local transmission iscompleted and which prevent local transmission until a full word countof local reception or until expiration of a delay sufficient to assurethat the remote station transmission has been completed. This delay maybe several times a normal multiplex signal sequence cycle, thethirty-two words in the example.

Assume for illustration that on starting the system both transmittersbegin to transmit andthat multiplexer 39 (the unit having failure timer193) is ahead of the other unit, unit 37. When 39 completes transmissionit starts its receiver which receives the residue of the signal from 37.Receiver 39 continues to receive as transmitter 37 completes itstransmission. Receiver 37 is set to receive but transmitter 39 is nottransmitting. Since transmitter 37 has stopped transmitting and receiver39 received only the terminal portion of its transmission the system isstalled. Timer 193 times out and starts 39 transmitting. At this timereceiver 37 has been conditioned to receive and, therefore, startsreceiving in synchronism with transmitter 39. Thereafter, synchronism ismaintained since transmitter 39 and receiver 37 complete their cyclessimultaneously and start their receiver and transmitter respectively atthe same time.

As another illustration,assume that both receivers started partiallythrough a receiving cycle. Neither transmitter would transmit and timer193 would time out in due course. Transmitter 39 would be started andwould fill receiver 37 so that as transmitter 39 continued transmitting,transmitter 37 would start. We thus would have the conditions firstmentioned and that sequence of events would proceed until a secondtiming out of failure timer 193 would place the stations in synchronism.

Other conditions which might exist where the stations were out ofsynchronism include both transmitting with transmitter 37 ahead oftransmitter 39; transmitter 39 ahead of receiver 37; transmitter 39behind receiver 37; receiver 39 ahead of transmitter 37; and

receiver 39 behind transmitter 37. In each instancethe sequences run toa time out of the failure timer and then run through the precedingsequences to achieve synchronization.

In order to be compatible with existing elevator circuitry it may benecessary to provide a buffer consisting of a voltage divider andcapacitor for each input line 114 to reduce the input voltage from thesignal applying switch associated therewith. Also, each output line 126may require a driver to raise the output voltage to a level compatiblewith the circuits to be controlled by the output signal. These arewell-known techniques and do not form part of the invention.

While specific circuit arrangements have been employed to illustratethis invention, it is to be appreciated that other circuits are withinthe skill of the art for achieving the functions and interrelationshipsof this invention. For example, the high and low signals transmittedcould be high frequency and low frequency signal bursts sequenced in themanner disclosed and be decoded by high and low pass filters.Accordingly, the above disclosure is to be read as illustrative and notin a limiting sense.

What is claimed is:

l. A control system for an elevator including an elevator car, acontroller for said car, and drive means for driving said car between aplurality of landings served thereby comprising a first station havingelevator controls; a second station having elevator controls; atransmission line coupling said first station and said second station; aplurality of signal inputs at said first station; means to read saidinputs individually in a predetermined order; a'transmitter at saidfirst station coupled to said transmission line for transmitting signalsfrom said reading means in the order said signals are read; a receivercoupled to said transmission line at said second station; a plurality ofsignal storage means at said second station; means to couple signalsfrom said transmission line individually to individual signal storagemeans in a predetermined order corresponding to the order said signalinputs are read by said reading means, said storage means correspondingto said signal inputs; and signal outputs at said second station fromsaid signal storage means.

2.. A control system according to claim It wherein said first station ison said elevator and said second station is associated with thecontroller remote from said elevator car; means on said car responsiveto car position coupled to one of said signal inputs to apply a signalthereto; and coupling means to said drive means from said signal outputof said second station for said storage means corresponding to said carposition responsive signal input.

3. A control system according to claim 1 wherein said car includes anentry; a closure for said entry; means sensing the position of saidclosure in said entry and applying signals responsive thereto to one ofsaid signal inputs; and coupling means to said controller forsaid carfrom said signal output at said second station corresponding to saidclosure position responsive signal input.

4. A control system according to claim 1 wherein said car includes anentry; a closure for said entry; controls for said closure for applyingsignals to one of said signal inputs; and coupling means to saidcontroller for said car from said signal output at said second stationcorresponding to said closure control signal input.

5. A control system according to claim ll wherein said car includesmeans for registering car calls for service to the landings bypassengers within said car for applying signals to said signal inputs;and coupling means to said controller for said car from said signaloutputs at said second station corresponding to said car call signalinputs.

6. A control system according to claim 1 including a plurality of meansfor generating different car operating signals mounted on said car,means coupling each of a plurality of said signal generating means torespective ones of said signal inputs as said first station; andcoupling means to said controller for said car from said signal outputsat said second station corresponding to said signal inputs for said caroperating signals.

7. A control system according to claim 6 including a traveling cableextending between said car and a fixed location in structure severed bythe car wherein said first station is on said elevator car and saidtransmission line is incorporated in said traveling cable.

8. A control system according to claim 1 including, means to sense thecompletion of the reading of predetermined inputs; and means to enable arepetition of the reading of said inputs individually in saidpredetermined order in response to said completion sensing means.

9. A control system according to claim 1 including encoding means toencode signals read by said signal reading means for transmission bysaid transmission line; and decoding means to decode encoded signalsreceived by said receiver to a form for application to said signalstorage means.

10. A control system according to claim 9 wherein said encoding anddecoding means are for binary sig' nals.

11. A control system according to claim ll including a plurality ofsignal inputs at said second station; means to read said inputs at saidsecond station individually in a predetermined order; a transmitter atsaid second station coupled to said transmission line for transmittingsignals from said reading means at said second station in the order saidsignals are read; a receiver coupled to said transmission line at saidfirst station; a plurality of signal storage means at said firststation; means at said first station to couple signals from saidtransmission line individually to individual signal storage means atsaid first station in a predetermined order as received by said receiverat said first station; signal outputs at said first station from saidsignal storage means at said first station; means for enabling saidtransmitter at said first station while inhibiting said receiver at saidfirst station; and means for enabling said transmitter at said secondstation while inhibiting said receiver at said second station.

12. A control system according to claim till including means forenabling said receiver at said first station while inhibiting saidtransmitter at said first station; and means for enabling said receiverat said second station while inhibiting said transmitter at said secondstation.

13. A control system for an elevator comprising a first station and asecond station; transmission line means coupling said first station andsaid second station; a transmitter at each station adapted to generate aregular cyclic sequence of signals for discrete elevator operatingfunctions; a receiver at each station adapted to receive a sequence ofsignals for discrete elevator operating functions corresponding to thesequence and functions of the signals generated by said transmitter ofthe station coupled thereto by said transmission line; and means tomaintain each received signal for said receivers until said signal isaltered during a regular cyclic sequence of signals from the transmitterfrom which it was received.

14. A control system according to claim 13 including a plurality ofsignal sources at each station for said signals for discrete elevatoroperating functions; signal encoding means at each station for encodingsignalsirom said respective sources for said respective transmitters;and signal decoding means at each station for decoding signals receivedby said respective receivers for application to said signal maintainingmeans.

15. A control system according to claim Ml including scanning means forsaid transmitter at each station for scanning said sources at saidstation; signal latchmeans for said transmitter actuated during aninitial portion of the scan of each source by said scanning means tolatch the currently scanned signal; and means enabling said encodingmeans during a portion of the scan of each source by said scanning meanswhich is subsequent to said initial portion to encode the latchedsignal.

16. A control system according to claim 13 wherein said transmitter atsaid each station and said receiving means at said station are connectedin parallel to said transmission line means.

17. A control system according to claim 16 including means to inhibitreception by the receiver at each station during transmission of signalsby said transmitter at said station.

18. A control system according to claim 16 including means to enablereception by the receiver at each station upon completion of eachtransmission of a cyclic sequence of signals by said transmitter at saidstation.

19. A control system according to claim 13 including a plurality ofsources of discrete elevator operating signals at each station; saidtransmitter at each station including means for scanning the sources atsaid station in a predetermined sequence; means at each station forencoding each signal as it is scanned; said receiver at each stationincluding means for scanning said signal maintaining means insynchronism with said scanning means of said transmitter at the oppositestation; and means at each station for decoding each signal received bysaid receiver.

20. A control system according to claim 19 including means to generateclocking signals, said clocking signals actuating said source scanningmeans; and means actuating said encoder in response to said clockingsignals and in synchronism with the scan of individual signal sources.

21. A control system according to claim 19 including means to define asignal characteristic of each encoded signal; and means for actuatingsaid signal maintaining scanning means in response to said definedsignal.

22. A control system according to claim 19 including means todefine asignal characteristic of each encoded signal; and means for actuatingsaid decoding means in response to said defined signal.

23. A control system according to claim 19 including means associatedwith the transmitter at each station to generate clocking signals; means'to advance said source scanning means in response to said clockingsignals; means to actuate said encoder in response to said clockingsignals and in synchronism with the scan of individual sources; means toproduce a signal characteristic of an encoded signal for each encodedsignal; means associated with the receiver at each station to advancesaid signal maintaining scanning means in response to saidcharacteristic signal from the transmitter at the opposite station; andmeans for actuating said decoding means in synchronism with the advanceof said receiver associated scanning means in response to saidcharacteristic signal.

24. A control system according to claim 13 including individualsequencing controls for said first and second stations for mutuallyexclusive enabling of said transmitter and receiver of each station.

25. A control system according to claim 13 including means to sense anabsence of synchronism in the sequence of signals transmitted by thetransmitter at one of said stations and the signals received by thereceiver at the station opposite said one station.

26. A control system according to claim 13 including means at eachstation for said transmitter at said station for sensing the completionof a cyclic sequence of signals generated by said transmitter; means ateach station for said receiver at said station for enabling saidreceiver at said station in response to completion of a cyclic sequenceof signals generated by said transmitter at said station; means at eachstation for said receiver at said station for sensing the completion ofreception by said receiver of a predetermined number of signalsgenerated by said transmitter at said opposite station; and means ateach station to recycle said sequence of signals generated by saidtransmitter for said station in response to the completion of receptionby said receiver at said station of said predetermined number ofsignals.

27. A control system according to claim 26 including a timer defining aninterval initiated upon enabling a receiver at a station and of a lengthexceeding the time required to complete reception by said receiver ofsaid predetermined number of signals; and means responsive to expirationof said interval without completion of reception of said predeterminednumber of signals to recycle said sequence of signals generated by saidtransmitter for said station.

28. In an elevator system including an elevator car movable in ahatchway, a source of a plurality of first control signals in said car,a control unit responsive to each of a plurality of second controlsignalsin said car;

a prime mover, a fixed controller for controlling said prime mover inresponse to each of said plurality of first control signals, a sourcefor said plurality of second control signals in said controller and acommunication system for sending said pluralities of first and sec ondcontrol signals in multiplexed coded binary form between said car andsaid controller, said communication system comprising a firsttransmitting means for said coded first control signals, a secondtransmitting means for said coded second control signals, a firstreceiving means responsive to each of, said coded first control signals,a second receiving means responsive to each of said coded second controlsignals and connecting means between said first transmitting means andsaid first receiving means and between said second transmitting meansand said second receiving means.

29. An elevator system according to claim 28 wherein said connectingmeans is a flexible transmission line having said first transmittingmeans and said second receiving means connected in parallel to one endthereof and having said second transmitting means and said firstreceiving means connected in parallel to the other end thereof.

30. An elevator system according to claim 28 wherein said transmittingmeans include means to generate a train of clock pulses, meansresponsive to said clock pulses for generating an enable signal andmeans responsive to said enable signal for coding each of said pluralityof control signals in sequence.

31. An elevator system according to claim 30 wherein said means forcoding includes multiplexing means responsive to said train ofclock-pulses for selecting in sequence each of said plurality of controlsignals, said control signals being either a binary l or a binary 0; andmeans responsive to said train of clock pulses and said selected controlsignal for generating a four pulse coded signal having as the first andfourth pulses binary 0, the second pulse binary 1" and the third pulsebinary 1 if said control signal is binary or binary 0 if said controlsignals is binary l. 32. An elevator system according to claim 30wherein said receiving means include means responsive to said codedcontrol signals for generating clock pulses, means responsive to saidclock pulses for generating an enable signal, means responsive to saidenable signal for decoding said coded control signals and means forstoring said decoded control signals.

33. An elevator system according to claim 32 wherein said means forgenerating clock pulses includes a timer with a timing period equal tothe duration of 1% pulses of said coded control signals, meansresponsive to the second pulse of said coded control said transmitter.

1. A control system for an elevator including an elevator car, acontroller for said car, and drive means for driving said car between aplurality of landings served thereby comprising a first statiOn havingelevator controls; a second station having elevator controls; atransmission line coupling said first station and said second station; aplurality of signal inputs at said first station; means to read saidinputs individually in a predetermined order; a transmitter at saidfirst station coupled to said transmission line for transmitting signalsfrom said reading means in the order said signals are read; a receivercoupled to said transmission line at said second station; a plurality ofsignal storage means at said second station; means to couple signalsfrom said transmission line individually to individual signal storagemeans in a predetermined order corresponding to the order said signalinputs are read by said reading means, said storage means correspondingto said signal inputs; and signal outputs at said second station fromsaid signal storage means.
 2. A control system according to claim 1wherein said first station is on said elevator and said second stationis associated with the controller remote from said elevator car; meanson said car responsive to car position coupled to one of said signalinputs to apply a signal thereto; and coupling means to said drive meansfrom said signal output of said second station for said storage meanscorresponding to said car position responsive signal input.
 3. A controlsystem according to claim 1 wherein said car includes an entry; aclosure for said entry; means sensing the position of said closure insaid entry and applying signals responsive thereto to one of said signalinputs; and coupling means to said controller for said car from saidsignal output at said second station corresponding to said closureposition responsive signal input.
 4. A control system according to claim1 wherein said car includes an entry; a closure for said entry; controlsfor said closure for applying signals to one of said signal inputs; andcoupling means to said controller for said car from said signal outputat said second station corresponding to said closure control signalinput.
 5. A control system according to claim 1 wherein said carincludes means for registering car calls for service to the landings bypassengers within said car for applying signals to said signal inputs;and coupling means to said controller for said car from said signaloutputs at said second station corresponding to said car call signalinputs.
 6. A control system according to claim 1 including a pluralityof means for generating different car operating signals mounted on saidcar, means coupling each of a plurality of said signal generating meansto respective ones of said signal inputs as said first station; andcoupling means to said controller for said car from said signal outputsat said second station corresponding to said signal inputs for said caroperating signals.
 7. A control system according to claim 6 including atraveling cable extending between said car and a fixed location instructure severed by the car wherein said first station is on saidelevator car and said transmission line is incorporated in saidtraveling cable.
 8. A control system according to claim 1 includingmeans to sense the completion of the reading of predetermined inputs;and means to enable a repetition of the reading of said inputsindividually in said predetermined order in response to said completionsensing means.
 9. A control system according to claim 1 includingencoding means to encode signals read by said signal reading means fortransmission by said transmission line; and decoding means to decodeencoded signals received by said receiver to a form for application tosaid signal storage means.
 10. A control system according to claim 9wherein said encoding and decoding means are for binary signals.
 11. Acontrol system according to claim 1 including a plurality of signalinputs at said second station; means to read said inputs at said secondstation individually in a predetermined order; a transmitter at saidsecond station coupled to said transMission line for transmittingsignals from said reading means at said second station in the order saidsignals are read; a receiver coupled to said transmission line at saidfirst station; a plurality of signal storage means at said firststation; means at said first station to couple signals from saidtransmission line individually to individual signal storage means atsaid first station in a predetermined order as received by said receiverat said first station; signal outputs at said first station from saidsignal storage means at said first station; means for enabling saidtransmitter at said first station while inhibiting said receiver at saidfirst station; and means for enabling said transmitter at said secondstation while inhibiting said receiver at said second station.
 12. Acontrol system according to claim 11 including means for enabling saidreceiver at said first station while inhibiting said transmitter at saidfirst station; and means for enabling said receiver at said secondstation while inhibiting said transmitter at said second station.
 13. Acontrol system for an elevator comprising a first station and a secondstation; transmission line means coupling said first station and saidsecond station; a transmitter at each station adapted to generate aregular cyclic sequence of signals for discrete elevator operatingfunctions; a receiver at each station adapted to receive a sequence ofsignals for discrete elevator operating functions corresponding to thesequence and functions of the signals generated by said transmitter ofthe station coupled thereto by said transmission line; and means tomaintain each received signal for said receivers until said signal isaltered during a regular cyclic sequence of signals from the transmitterfrom which it was received.
 14. A control system according to claim 13including a plurality of signal sources at each station for said signalsfor discrete elevator operating functions; signal encoding means at eachstation for encoding signals from said respective sources for saidrespective transmitters; and signal decoding means at each station fordecoding signals received by said respective receivers for applicationto said signal maintaining means.
 15. A control system according toclaim 14 including scanning means for said transmitter at each stationfor scanning said sources at said station; signal latch means for saidtransmitter actuated during an initial portion of the scan of eachsource by said scanning means to latch the currently scanned signal; andmeans enabling said encoding means during a portion of the scan of eachsource by said scanning means which is subsequent to said initialportion to encode the latched signal.
 16. A control system according toclaim 13 wherein said transmitter at said each station and saidreceiving means at said station are connected in parallel to saidtransmission line means.
 17. A control system according to claim 16including means to inhibit reception by the receiver at each stationduring transmission of signals by said transmitter at said station. 18.A control system according to claim 16 including means to enablereception by the receiver at each station upon completion of eachtransmission of a cyclic sequence of signals by said transmitter at saidstation.
 19. A control system according to claim 13 including aplurality of sources of discrete elevator operating signals at eachstation; said transmitter at each station including means for scanningthe sources at said station in a predetermined sequence; means at eachstation for encoding each signal as it is scanned; said receiver at eachstation including means for scanning said signal maintaining means insynchronism with said scanning means of said transmitter at the oppositestation; and means at each station for decoding each signal received bysaid receiver.
 20. A control system according to claim 19 includingmeans to generate clocking signals, said clocking signals actuating saidsource scanning meAns; and means actuating said encoder in response tosaid clocking signals and in synchronism with the scan of individualsignal sources.
 21. A control system according to claim 19 includingmeans to define a signal characteristic of each encoded signal; andmeans for actuating said signal maintaining scanning means in responseto said defined signal.
 22. A control system according to claim 19including means to define a signal characteristic of each encodedsignal; and means for actuating said decoding means in response to saiddefined signal.
 23. A control system according to claim 19 includingmeans associated with the transmitter at each station to generateclocking signals; means to advance said source scanning means inresponse to said clocking signals; means to actuate said encoder inresponse to said clocking signals and in synchronism with the scan ofindividual sources; means to produce a signal characteristic of anencoded signal for each encoded signal; means associated with thereceiver at each station to advance said signal maintaining scanningmeans in response to said characteristic signal from the transmitter atthe opposite station; and means for actuating said decoding means insynchronism with the advance of said receiver associated scanning meansin response to said characteristic signal.
 24. A control systemaccording to claim 13 including individual sequencing controls for saidfirst and second stations for mutually exclusive enabling of saidtransmitter and receiver of each station.
 25. A control system accordingto claim 13 including means to sense an absence of synchronism in thesequence of signals transmitted by the transmitter at one of saidstations and the signals received by the receiver at the stationopposite said one station.
 26. A control system according to claim 13including means at each station for said transmitter at said station forsensing the completion of a cyclic sequence of signals generated by saidtransmitter; means at each station for said receiver at said station forenabling said receiver at said station in response to completion of acyclic sequence of signals generated by said transmitter at saidstation; means at each station for said receiver at said station forsensing the completion of reception by said receiver of a predeterminednumber of signals generated by said transmitter at said oppositestation; and means at each station to recycle said sequence of signalsgenerated by said transmitter for said station in response to thecompletion of reception by said receiver at said station of saidpredetermined number of signals.
 27. A control system according to claim26 including a timer defining an interval initiated upon enabling areceiver at a station and of a length exceeding the time required tocomplete reception by said receiver of said predetermined number ofsignals; and means responsive to expiration of said interval withoutcompletion of reception of said predetermined number of signals torecycle said sequence of signals generated by said transmitter for saidstation.
 28. In an elevator system including an elevator car movable ina hatchway, a source of a plurality of first control signals in saidcar, a control unit responsive to each of a plurality of second controlsignals in said car, a prime mover, a fixed controller for controllingsaid prime mover in response to each of said plurality of first controlsignals, a source for said plurality of second control signals in saidcontroller and a communication system for sending said pluralities offirst and second control signals in multiplexed coded binary formbetween said car and said controller, said communication systemcomprising a first transmitting means for said coded first controlsignals, a second transmitting means for said coded second controlsignals, a first receiving means responsive to each of said coded firstcontrol signals, a second receiving means responsive to each of saidcoded second control signals and connecting meanS between said firsttransmitting means and said first receiving means and between saidsecond transmitting means and said second receiving means.
 29. Anelevator system according to claim 28 wherein said connecting means is aflexible transmission line having said first transmitting means and saidsecond receiving means connected in parallel to one end thereof andhaving said second transmitting means and said first receiving meansconnected in parallel to the other end thereof.
 30. An elevator systemaccording to claim 28 wherein said transmitting means include means togenerate a train of clock pulses, means responsive to said clock pulsesfor generating an enable signal and means responsive to said enablesignal for coding each of said plurality of control signals in sequence.31. An elevator system according to claim 30 wherein said means forcoding includes multiplexing means responsive to said train of clockpulses for selecting in sequence each of said plurality of controlsignals, said control signals being either a binary ''''1'''' or abinary ''''0''''; and means responsive to said train of clock pulses andsaid selected control signal for generating a four pulse coded signalhaving as the first and fourth pulses binary ''''0'''', the second pulsebinary ''''1'''' and the third pulse binary ''''1'''' if said controlsignal is binary ''''0'''' or binary ''''0'''' if said control signalsis binary ''''1''''.
 32. An elevator system according to claim 30wherein said receiving means include means responsive to said codedcontrol signals for generating clock pulses, means responsive to saidclock pulses for generating an enable signal, means responsive to saidenable signal for decoding said coded control signals and means forstoring said decoded control signals.
 33. An elevator system accordingto claim 32 wherein said means for generating clock pulses includes atimer with a timing period equal to the duration of 1 1/2 pulses of saidcoded control signals, means responsive to the second pulse of saidcoded control signals for initiating said timing period; and meansresponsive to the end of said timing period for generating a clockpulse.
 34. A control system according to claim 13 including a timerdefining an interval initiated upon enabling a receiver at a station andof a length exceeding the time required to complete reception by saidreceiver of a predetermined number of said signals; and means responsiveto expiration of said interval without reception of signals to recyclesaid transmitter for said station to transmit the sequence of signalsgenerated by said transmitter.